Micro LED Optical Interconnects: Breaking the Copper-Optics Trade-off

In 2025, the ACM flagship conference SIGCOMM will be held from September 8–11, and the list of accepted papers has already been announced. Among them, the Microsoft Research team published a paper titled “MOSAIC: Breaking the Optics versus Copper Trade-off with a Wide-and-Slow Architecture and MicroLEDs.” This paper introduces an optical link technology based on MicroLEDs. Through architectural restructuring and component-level innovations, the technology is expected to break the inherent trade-off between copper and optical links in data center networks, offering a viable solution for next-generation interconnects that deliver high bandwidth, low power consumption, and high reliability.

1. The Link Dilemma in Data Center Networks: The Inherent Conflict Between Copper and Optics

Current data center interconnect technologies consistently face the triple challenge of transmission distance, power consumption, and reliability:

• Copper linksprovide high power efficiency and strong reliability, but their transmission distance is extremely short (only less than 2 meters), limiting their application to intra-rack connections only.
• Mainstream optical links(such as Active Optical Cables, AOCs) can support transmission over tens of meters but come with significantly higher power consumption and much higher failure rates—their power draw is several times greater than copper, while their failure rate is more than 100× higher.

  

As network speeds advance to 800 Gbps and above, this contradiction becomes even sharper:

• The transmission distance of copper cables continues to shrink with speed increases (next-generation 1.6 Tbps copper cablesare expected to support less than 1 meter).
• The power consumption of optical links rises dramatically with higher speeds (an 800 Gbps AOCconsumes 9.8–12 W per end).
• High-speed transmission further accelerates the aging and failure risk of optical components, creating the threat of a “network wall”that may lead to increased deployment costs, uncontrolled power usage, and reduced reliability in data centers.

Case in point: AI clusters
For example, in the NVIDIA NVL72 pod, which interconnects 72 B200 GPUs, the excessive power consumption of optical links (adding about 20 kW per rack) and their high failure rates (in a 100,000-GPU cluster, a link failure occurs every 6–12 hours) force the system to rely on copper cabling. This results in all 72 GPUs being confined to a single rack, driving rack power density up to 120 kW per rack, requiring complex liquid cooling solutions and causing deployment delays. This predicament highlights the urgent need for new interconnect technologies.

2. Core of MOSAIC Technology: Breaking the Trade-Off with a Wide-and-Slow Architecture

The core innovation of MOSAIC (Wide-and-Slow optical interconnect technology) lies in overturning the traditional “Narrow-and-Fast (NaF)” paradigm by adopting a “Wide-and-Slow (WaS)” architecture. Instead of relying on a small number of high-speed channels, MOSAIC employs hundreds of parallel low-speed optical channels, achieving the goals of long-distance transmission, low power consumption, and high reliability.

2.1 Architectural Innovation: From “Fewer but Faster” to “More but Slower”

Traditional interconnects (both copper and optical) have been based on the NaF architecture. For instance, an 800 Gbps link typically uses eight 100 Gbps high-speed channels. This design faces limitations: in copper cables, high-speed signals suffer from severe signal integrity issues that limit distance; in optical links, high-power components (laser drivers, ADC/DAC, DSP) and complex error correction mechanisms result in high power consumption and lower reliability.

MOSAIC shifts to the WaS architecture: replacing a few high-speed channels with hundreds of parallel low-speed optical ones. For example, with 2 Gbps per channel, 400 channels can deliver 800 Gbps aggregate throughput. This approach is inspired by the parallel low-speed philosophy used in memory and chip buses, offering natural advantages of low power, high reliability, and simpler design.

In fact, memory and chip interconnects commonly adopt WaS schemes: multiple low-speed parallel channels reduce power consumption. Figure 2 shows the relationship between channel speed and energy efficiency (pJ/bit, equivalent to W/Tbps) across different chip interconnect technologies, comparing traditional high-speed serial links (XSR) with WaS solutions (UCIe, BoW, OpenHBI). Results indicate that the lower the per-channel data rate, the higher the overall energy efficiency. Beyond power savings, as noted earlier, lower speeds also reduce channel loss in copper links and improve reliability in optical links.

Given these advantages, one might wonder: why did network interconnect technologies diverge from memory/chip interconnects and adopt the NaF design instead?

The reason lies in basic physical limitations. Unlike board-level traces where dense routing can be achieved through fine-pitch wiring, meter-scale copper cables face electromagnetic interference (EMI) and crosstalk when too many channels are placed in close proximity. Thus, beyond a certain point, scaling channel count becomes impractical, forcing designers toward fewer but faster serial channels to maximize bandwidth.

Optical links, while immune to EMI, face other challenges: the scalability of lasers is poor. A single communication-grade laser typically consumes tens to hundreds of milliwatts, and scaling to hundreds of lasers results in unacceptably high power draw. Furthermore, packaging hundreds of lasers and fibers brings severe reliability and manufacturing challenges. Finally, because lasers themselves are not inherently reliable, increasing the count proportionally raises the system failure rate.

By adopting microLEDs as light sources, MOSAIC overcomes these limitations, providing a practical path for WaS optical interconnects. Unlike copper, microLED-based optical transmission eliminates EMI, allowing dense packing of channels without interference. Each microLED consumes only a few hundred microwatts—orders of magnitude lower than lasers—making scaling to hundreds of channels feasible without excessive power draw. A single monolithically integrated microLED array can host over 400 channels within 1 mm². Coupled with MOSAIC’s compact multicore imaging fiber, this enables ultra-high-density solutions with simplified packaging. Unlike lasers, which require temperature control and active wavelength stabilization, microLEDs are inherently more robust and can incorporate redundant channels in arrays to further enhance reliability.

2.2 Core Components: Three Breakthroughs Enabling Implementation

• Directly Modulated microLEDs:
  Instead of traditional lasers, MOSAIC uses microLEDs—originally designed for displays—as light sources. Each microLED, only a few to tens of microns in size, can be modulated at several Gbps with a simple ON–OFF scheme. Fabricated as arrays, a single chip can integrate dozens to hundreds of devices, meeting aggregation needs (e.g., a 20 × 20 array achieving 800 Gbps). Compared with lasers, microLEDs consume only a few hundred microwatts (1/100–1/1000 of a laser), are structurally simpler, temperature-insensitive, and significantly more reliable.

• Multicore Imaging Fiber:
  Borrowed from medical endoscopy applications, multicore imaging fiber contains thousands of fiber cores in a single strand, solving the problem of needing hundreds of fibers for hundreds of channels. Within a single fiber, transmission characteristics (loss, dispersion) are highly uniform, and length variations are minimal (a 1 cm mismatch causes only a 50 ps delay—just 10% of a 2 Gbps bit period). Thus, channel-to-channel skew can be neglected.

• Low-Power Analog Backend:
  Leveraging the low-speed nature of each channel, the design is simplified by using NRZ coding (two levels: ON/OFF), avoiding complex DSP, ADC/DAC, and CDR circuits. Basic analog equalization compensates for channel impairments, drastically cutting power. For an 800 Gbps link, end-to-end power consumption is only 3.1–5.3 W—56–68% lower than conventional optical interconnects.

2.3 Performance Advantages: Surpassing Traditional Links

MOSAIC combines the strengths of copper and optical links. It achieves transmission distances of up to 50 m (over 10× longer than copper), reduces power consumption by up to 68%, and provides 100× greater reliability than current optical solutions. It supports 800 Gbps and can scale to 1.6 Tbps or 3.2 Tbps by increasing channel counts or boosting per-channel rates (to 4–8 Gbps).

Furthermore, MOSAIC is compatible with existing QSFP/OSFP packaging and electrical interfaces such as PCIe, making it a drop-in replacement for current interconnects without requiring modifications to servers or switches.

3. Technical Details: Addressing Engineering Challenges of the “Wide-and-Slow” Architecture

3.1 Optical Challenges of microLEDs and Solutions

MicroLEDs face two main optical challenges: beam divergence (difficult to couple into fibers) and broad spectral width (susceptible to dispersion). MOSAIC addresses these through targeted design:

• TIR Microlens Design
  As Lambertian emitters, microLEDs exhibit beam divergence up to ±90°. Conventional microlenses have poor coupling efficiency under such conditions. MOSAIC developed custom Total Internal Reflection (TIR) microlenses that collimate the beam into a ±12° cone, more than doubling coupling efficiency while suppressing inter-channel crosstalk.

  

• Low-Power Analog Dispersion Compensation
  The spectral width of microLEDs can reach several tens of nanometers (far broader than the sub-picometer linewidth of lasers), making them highly susceptible to chromatic dispersion. Leveraging the low-speed transmission characteristics, MOSAIC uses simple analog equalization circuits to compensate for dispersion, eliminating the need for complex DSP. Stable transmission is achieved at 2 Gbps per channel.

3.2 Channel Multiplexing with Multicore Imaging Fiber

To avoid the complexity of using hundreds of fibers for hundreds of channels, MOSAIC adopts a “single microLED-to-multiple cores” mapping strategy. By utilizing the thousands of cores in a multicore imaging fiber, a single microLED’s signal can be distributed across multiple fiber cores. This greatly reduces alignment precision requirements and simplifies packaging. The uniform transmission characteristics (loss, dispersion) and minimal length differences among the cores ensure a stable foundation for parallel transmission.

3.3 Simplification and Optimization of Electronic Design

MOSAIC’s electronic backend takes full advantage of the low-speed channel characteristics:

• Simplified Encoding and Error Correction
  Using NRZ encoding (two levels) instead of PAM-4 reduces SNR requirements and eliminates the need for costly ADC/DACs. Given the naturally low bit-error rate (BER), no additional heavy FEC logic is required; standard link-layer FEC suffices.

• No CDR Circuits
  Clock signals are transmitted via an additional control channel, eliminating the need for clock data recovery (CDR) at the receiver. This reduces both power and area costs. For example, adding one clock channel among 400 channels increases cost by only 0.25%.

3.4 Over-Provisioning of Channels: Enhancing Reliability and Efficiency

The low-cost redundancy of the “Wide-and-Slow” architecture makes optimization feasible:

• Fault-Tolerant Mechanisms
  A dual-layer scheme combining ECC and hot spares is used. Lightweight ECC (e.g., Hamming codes) encodes data channels (e.g., 400 data channels + 60 parity channels, ~15% overhead), masking single-channel failures. Hot standby channels allow instant failover, ensuring zero downtime and keeping BER below the FEC threshold (2 × 10⁻⁴).

• In-Band Control Plane
  Redundant channels are used for link training, negotiation, and telemetry without consuming data bandwidth. Clock signals transmitted over control channels further replace traditional CDR circuits, saving power.

Power Balancing
FIFO queues monitor data load, shutting down idle channels during low traffic and reactivating them when demand rises. This allows power consumption to scale with actual traffic needs. In asymmetric workloads such as AI inference (read-heavy vs. write-light), this approach significantly reduces idle power consumption.

4. Prototype Validation and Scalability Evaluation

4.1 Performance of the 100-Channel Prototype System

The team built an end-to-end prototype system with the following core configuration: a 10 × 10 microLED array and CMOS sensor chip, custom TIR microlens array, multicore imaging fiber, and an HTG-940 FPGA-based analog electronic backend. Experimental results demonstrated:

• Baseline Transmission Performance
  At a distance of 20 meters, each channel achieved 2 Gbps transmission with a median Bit Error Rate (BER) of <2 × 10⁻⁸, with all channels remaining below the Ethernet FEC threshold (2 × 10⁻⁴). At 30 meters, reducing the per-channel rate to 1.6 Gbps still satisfied the FEC requirement.

  

  

• Fault Tolerance Verification
  In a 10 Gbps Ethernet experiment (6 data channels + 5 parity channels), two channels were deliberately shut down. The “ECC + hot spare” mechanism maintained stable BER and uninterrupted links. Using ECC alone, however, the system failed upon the second fault.

  

  

• Microlens Effectiveness
  The TIR microlens compressed the microLED beam divergence from ±90° to ±12°, doubling coupling efficiency and significantly suppressing inter-channel crosstalk.

4.2 Scalability Simulation and Expansion Potential

The research team validated MOSAIC’s scalability potential through simulations:

• • 800 Gbps Pluggable Module
    With 460 channels (including 15% redundancy), simulations showed that 2 Gbps per channel transmission could be achieved over 50 meters with BER <10⁻⁶. At 10 meters, up to 8 Gbps per channel is supported.

    

  • Reliability Simulation
    With 100 redundant channels, even if the per-channel failure rate (FIT) equals 1, the overall link FIT can be reduced to <20—comparable to copper interconnect reliability. By contrast, traditional optical interconnects typically exhibit FIT in the hundreds.

    

    

  • Coupling and Crosstalk
    Zemax optical simulations indicated that with 460 channels transmitted through a multicore fiber, beam separation remained clear, crosstalk was negligible, and received optical power matched that of the prototype.

  • Engineering Implementation Analysis
    Due to prototype fabrication limitations (e.g., wire bonding, discrete lenses, and electronics), compromises had to be made in channel count and performance. For mass-production modules, the team proposed a miniaturized, integrated design (concept shown in Figure 10), whose feasibility has been confirmed by suppliers. Compared with the prototype, this design delivers significant improvements in both performance and efficiency:

    1. Integrated lenses and custom fiber couplers dramatically improve coupling efficiency and emission conditions while reducing modal dispersion.

    2. All drivers and TIAs are integrated onto a single CMOS chip, with both the microLED and CMOS sensor arrays vertically bonded on top. This configuration (i) shortens electrical interconnect lengths significantly and (ii) eliminates wire-bond pitch constraints, enabling the use of smaller-pitch microLEDs to enhance overall system performance.

       

5. Power Consumption and Cost Analysis

5.1 Significant Power Efficiency Advantages

Compared with traditional 800 Gbps Active Optical Cables (AOCs), MOSAIC demonstrates substantial reductions in power consumption:

• Traditional Optical Link: End-to-end power consumption is 9.8–12 W, including DSP/CDR (3.5 W), lasers and drivers (4.7 W), host interface (0.2–2.4 W), and MCU/DC-DC (1.4 W).

• MOSAIC Link: End-to-end power consumption is only 3.1–5.3 W, including digital backend (0.4 W), microLEDs and drivers (1.2 W), host interface (0.2–2.4 W), and MCU/DC-DC (1.3 W)—a 56–68% reduction compared with traditional optical solutions.

• Future Expansion: A 1.6 Tbps MOSAIC link is projected to consume 10.6 W, far below the 23–25 W required by conventional designs.

5.2 Cost Control Potential

MOSAIC also offers strong cost-reduction potential through design choices and ecosystem leverage:

• No requirement for advanced process chips (eliminates the need for complex DSP).

• Utilization of the mature microLED and CMOS sensor manufacturing ecosystem.

• Multicore imaging fiber simplifies cabling and reduces material and assembly costs.

• Over-provisioning of channels improves yield, lowering overall system cost.

Taken together, these factors suggest that MOSAIC’s total cost could be lower than that of traditional optical interconnects, while delivering superior efficiency and reliability.

6. Application Prospects: Reshaping the Data Center Technology Ecosystem

6.1 Network Architecture Optimization

The limited transmission distance of copper cables severely constrains network architectures and topologies. For example, Top-of-Rack (ToR) switches are typically deployed because copper cannot span longer distances. Similarly, although 3D torus topologies are not optimal in terms of bisection bandwidth, they are often used in high-performance computing (HPC) clusters (such as Google TPU clusters or Amazon Trainium) because they are compatible with short copper interconnects.

MOSAIC’s 50-meter transmission capability breaks this distance barrier, enabling much greater flexibility in network design. For instance, eliminating ToR switches becomes feasible, allowing servers to connect directly to Row Switches or End-of-Row Switches. This reduces both network latency and hardware costs, while improving reliability by removing the ToR as a single point of failure.

Traditional optical links cannot achieve these benefits due to higher power consumption, cost, and reliability overheads. By contrast, MOSAIC makes fully non-blocking topologies more practical, potentially simplifying congestion control protocols. Its longer-reach links also enable advanced topologies such as multi-dimensional torus, dragonfly, and hypercube to become feasible, since designers are no longer constrained by short copper or the high cost and complexity of existing optical solutions. Overall, MOSAIC significantly expands the design space for customized, application-optimized networks.

6.2 GPU and Memory Architecture Innovations

• GPU Disaggregation: Large multi-die GPUs (e.g., NVIDIA Rubin Ultra with 4-chip packaging) can be split into smaller “LiteGPU” units, interconnected through low-power optical links. This reduces manufacturing complexity and power density.

• Memory Disaggregation: With its low-latency characteristics (requiring no FEC or DSP, only a few nanoseconds of delay), MOSAIC supports separating memory from compute resources. This reduces dependence on costly 3D-stacked HBM and allows GPUs to access larger pools of available memory.

6.3 AI Cluster Efficiency Improvement

MOSAIC enables high-speed interconnection across much larger GPU clusters, enhancing collective communication efficiency and accelerating both training and inference. Coupled with dynamic resource aggregation, it supports “elastic computing,” improving overall resource utilization and cluster efficiency.

7. Related Work

• Silicon Photonics
  Silicon photonics, with its advantages of high integration and CMOS compatibility, has attracted significant interest in recent years from companies within the CMOS ecosystem (e.g., GlobalFoundries and TSMC). Although this technology offers some cost savings due to CMOS ecosystem maturity, it still relies on the “Narrow-and-Fast” architecture, and therefore continues to face challenges in power consumption, scalability, and reliability.

• Co-Packaged Optics (CPO)
  This work primarily focuses on pluggable transceivers, as they remain the mainstream solution adopted by the industry. Pluggable modules offer high flexibility by allowing independent selection of transceivers separate from NIC/switch vendors, enabling horizontal integration across suppliers. However, they require long electrical traces to deliver signals from host chips (e.g., NICs or GPUs) to the front panel, which increasingly drives up power consumption.

  CPO addresses this by integrating optical transceivers directly into the same package as the host chip, which, according to recent industry estimates, can reduce power consumption by as much as 25–30%. MOSAIC is fully compatible with this configuration. In fact, as illustrated in Figure 8, MOSAIC’s advantages become even more evident when paired with CPO, since it can leverage low data rates of chip-to-chip interconnects for direct microLED modulation, without requiring the high-speed conversion needed by existing technologies.

• MicroLED-Based Communications
  While microLEDs were originally developed for display applications, prior proposals in the literature have explored their use in free-space communications and short-range chip-to-chip links. By contrast, MOSAIC targets longer-reach fiber-based transmission (up to 50 meters) to support rack-to-rack connectivity in data centers. This requires addressing a distinct set of challenges, such as fiber impairments (dispersion, modal dispersion) and coupling losses, which in turn necessitate new microLED optimizations and system-level design choices.

  MOSAIC further introduces high-reliability mechanisms, improved alignment tolerance, and novel microlens designs for efficient fiber coupling. Finally, while earlier research mainly focused on single-channel demonstrators in free-space or ultra-short waveguide environments, this work validates MOSAIC with a 100-channel prototype over fiber lengths up to 30 meters.

8. Conclusion

Microsoft Research’s MOSAIC technology leverages a “Wide-and-Slow” architecture combined with microLED innovations to overcome the inherent trade-offs between optical and copper interconnects in data centers. With its long reach (50 m), low power consumption (68% reduction), high reliability (100× improvement), and compatibility with existing infrastructure, MOSAIC provides a promising practical solution for next-generation data center networks.